1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device. The device according to the present invention is applicable to an erasable programmable read only memory (EPROM).
2. Description of the Related Art
In general, in an EPROM having a floating gate, programming of data "0" or "1" is carried out by charging or discharging the floating gate of a memory cell transistor. A large or small value of the electrons accumulated in the floating gate of the memory cell transistor is revealed as a large or small threshold value of the memory cell transistor. Therefore, it is possible to read data "0" or "1" of the memory cell by detecting whether the current flowing in response to an application of control gate voltage is small or large.
However, the electrons of the floating gate of the memory cell transistor tends to decrease with a lapse of time, and the threshold value of the memory cell transistor having a charged floating gate tends to approach that of a memory cell transistor having a discharged floating gate. Thus, the current reading of a memory cell transistor for data "0" is increased to approach the case for a memory cell transistor for data "1", and, as a result, an erroneous decision on the state of the memory cell transistor as data not being programmed may occur. This undesirably deteriorates the reliability of the system using an EPROM.